Domino circuits are commonly used in high-frequency microprocessor designs because the propagation delay through a domino circuit is generally less than the propagation delay through a functionally-equivalent complementary static circuit. However, domino circuits introduce several complications. Each domino gate requires a clocked PFET precharge device to precharge the gates internal dynamic node to a high voltage potential. A high DC current can result during precharge as illustrated by FIG. 1 when the PFET precharge device and the series NFET devices in the NFET tree are simultaneously conducting. Typically, a clocked NFET evaluation or foot device is added to each domino gate to break the conduction path during precharge (See U.S. Pat. No. 5,532,625 issued Jul. 2, 1996 to Sun Microsystems' S. Rajivan). Such a device prevents excessive DC current and speeds up the precharge of the dynamic node as shown in FIG. 1. However, this evaluation device adds one more NFET device to the NFET stack which increases the resistance of the dynamic node to ground discharge path resulting in greater propagation delay through the domino gate. The evaluation device also introduces greater clock load and higher chip power.